Module : Computer Architecture
| Semestre 4 CP | VHS C/TD/TP |
VHH Total C/TD/TP |
V.H. Hebdomadaire | Coef | Crédits | ||
|---|---|---|---|---|---|---|---|
| C | TD | TP | |||||
| UE Fondamentales 4.1 | 67.5 | 4.5 | 1.5 | 1.5 | 1.5 | 3 | 5 |
Course Description :
This course provides an introduction to computer organisation, systems programming and the hardware/software interface. Topics include instruction sets, computer arithmetic, datapath design, data formats, addressing modes, memory hierarchies including caches and virtual memory, I/O devices, bus-based I/O systems, and multicore architectures. Students learn assembly language programming and design a pipelined RISC processor.
Prerequisite: Computer Architecture I, Data Structures and Algorithms
Evaluation Method: Coursework (40%) + Final Exam (60%)
Course Content
- Introduction of RISC-V Architecture
- RISC-V Instruction Set
- RISC-V Programming Model
- RISC-V: Processor Design
- Pipelining
- Cache Management
- Virtual Memory
- I/O & interrupts
- Advanced Computer Architecture (Optional)
References
- John L. Hennessy, David A. Patterson, Computer Organization and Design. The Hardware/Software. Interface: RISC-V Edition. 2nd Edition. 2020.